This invention is in the field of integrated circuit electrical testing. Embodiments of this invention are more specifically directed to the screening of ferroelectric memory cells that are potentially of weak long term reliability.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example placing capacitors above the transistor level, between overlying levels of metal conductors.
Ferroelectric technology is now utilized in non-volatile solid-state read/write random access memory (RAM) devices. These memory devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, are now commonplace in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers, defibrillators, and monitoring devices, due to the ultra-low power consumption of FRAM memory. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T-2C (two transistor, two capacitor) cells in which the two ferroelectric capacitors in a cell are polarized to complementary states. Another type of FRAM cell is based on the well-known “6T” CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors. Ferroelectric cells constructed in a 1T-1C (one transistor, one capacitor) arrangement, similar to conventional dynamic RAM memory cells, are attractive because of their small chip area, but at a cost of less robust read performance than the larger area 2T-2C and 6T cell types.
FIG. 1a illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor between its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. While the ferroelectric capacitor has a linear capacitance, by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material), it also exhibits significant polarization capacitance (i.e., charge storage) in response to changes in polarization state that occurs upon application of a polarizing voltage. For example, referring to FIG. 1a, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), reflecting the storage of polarization charge in the capacitor in response to the change of polarization state by the voltage exceeding coercive voltage Vα. On the other hand, a capacitor that already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned in the direction of the applied coercive voltage, causing little additional polarization charge to be stored. As will be evident from the following description, a stored logic state is read by interrogating the capacitance of the ferroelectric capacitors to discern its polarization state.
FIG. 1b illustrates, in cross-section, a typical construction of a portion of an integrated circuit including a ferroelectric capacitor and an n-channel metal-oxide-semiconductor (MOS) transistor. In this arrangement, a MOS transistor is realized at the surface of p-type substrate 10 (or well), at an active region disposed between isolation dielectric structures 15 formed by shallow trench isolation in this example. N+ source/drain regions 14 are formed into substrate 10 on opposing sides of polysilicon gate element 16 in a self-aligned manner. Gate element 16 is separated from the surface of the active region by gate dielectric 17, thus forming the transistor. Sidewall spacers 19 on the sides of gate element 16 are useful in forming source/drain region extensions, as known in the art. A ferroelectric capacitor is formed in this structure by a ferroelectric stack including conductive plates 20a, 20b (formed of an elemental metal, or a conductive metal compound such as a metal nitride, conductive metal oxide, or a silicide, or a stack of two or more of these layers) between which ferroelectric material 22 is disposed. In this example, ferroelectric material 22 consists of PZT. Bottom conductive plate 20a is connected to the source/drain region 14 by conductive plug 18 formed into a contact opening etched through dielectric film 13. As typical in conventional process flows, passivation films 24, 25, 26 (e.g., of aluminum oxide, silicon nitride formed by high-density plasma, and CVD silicon nitride, respectively) are deposited over the ferroelectric capacitor structure to minimize hydrogen contamination of ferroelectric material 22.
FIG. 2a illustrates a typical arrangement of a conventional 1T-1C FRAM cell 2jk, which represents a single memory cell residing in a row j and a column k of an array of similar cells 2. Cell 2jk includes n-channel pass transistor 4 and ferroelectric capacitor 6. The source/drain path of transistor 4 is connected between bit line BLk for column k of the array, and the top plate of ferroelectric capacitor 6; the gate of transistor 4 is controlled by word line WLj for row j of the array. The bottom plate of ferroelectric capacitor 6 is connected to plate line PL, which may be in common for all cells 2 in the array (or in a particular portion of the array, depending on the architecture). Those skilled in the art will recognize that 1T-1C FRAM cells are constructed similarly as conventional dynamic RAM memory cells.
FIG. 2b illustrates the arrangement of cell 2jk of FIG. 2a within an FRAM device, particularly in the read context. In this example, sense amplifier 8 is coupled to bit line BLk, and operates to compare the bit line voltage developed by read current iR to a reference voltage VREF generated by reference voltage generator circuit 9. As typical in the art for 1T-1C memory cells, the polarization state that exhibits the higher capacitance when sensed, which in this case is the “−1” polarization state, will be considered as the “1” data state, and the lower capacitance “+1” polarization state will be considered as the “0” data state. Cell 2jk is written by applying voltages to plate line PL and bit line BLk that, with word line WLj energized, polarizes capacitor 6 into the desired polarization state. In this example, a “0” data state corresponding to the “+1” polarization state of FIG. 1 is written by the application of a low voltage (Vss) to bit line BLk, turning on word line WLj, and then raising plate line PL to a high voltage (Vcc). Conversely, a “1” data state corresponding to the “−1” polarization state is written by the application of a low voltage (Vss) to plate line PL, turning on word line WLj, and then raising bit line BLk to a high voltage (Vcc).
The read operation of cell 2jk begins with the precharging of bit line BLk to a low voltage (e.g., Vss). As shown in FIG. 2c, once bit line BLk is precharged, word line WLj is energized to turn on transistor 4 and couple capacitor 6 to bit line BLk. The voltage of plate line PL from the low voltage Vss is then raised to the high voltage Vcc to interrogate the polarization capacitance of capacitor 6, according to the hysteresis diagram of FIG. 1. Specifically, the energizing of plate line PL induces a read current iR onto bit line BLk to develop a voltage on bit line BLk. As known in the art, the voltage level developed on bit line BLk depends on the capacitance exhibited by ferroelectric capacitor 6 in cell 2jk relative to the bit line capacitance. If capacitor 6 is in the “+1” polarization state, the read current iR will be relatively low and will thus develop a relatively low level bit line voltage V(0) as shown in FIG. 2c. Conversely, the “−1” polarization state of capacitor 6 will result in a relatively strong read current iR, and a higher level voltage V(1) at bit line BLk.
According to an “after-pulse sensing” approach as shown in FIG. 2c, sense amplifier 8 is activated at time tSA_ap, after the plate line PL pulse, at which time sense amplifier 8 compares the bit line voltage with the reference voltage VREF from reference voltage generator 9. To discern the stored data state, reference voltage VREF is set to a voltage between the expected low and high data state levels V(0), V(1), respectively (i.e., within the window ΔV of FIG. 2b). Following time tSA_ap, sense amplifier 8 drives bit line BLk to a full logic “1” level in response to detecting the higher bit line voltage V(1), and to a full logic “0” level in response to detecting the lower bit line voltage V(0), as shown in FIG. 2c. Another sensing approach, referred to as “on-pulse” sensing may alternatively be used; in this approach, sense amplifier 8 is activated during the plate line pulse, for example at time tSA_op as shown in FIG. 2c. 
By way of further background, copending and commonly assigned U.S. Patent Application Publication US 2015/0357050, incorporated herein by reference, describes a data retention reliability screen of FRAM cells in which a reference voltage level for the read of a high polarization capacitance data state (e.g., a “1” state) is determined for each integrated circuit being tested. A number of FRAM cells in the integrated circuit are programmed to the “1” data state, and then read at an elevated temperature. The number of failing cells is compared against a pass/fail threshold to determine whether that integrated circuit is vulnerable to long-term data retention failure.
By way of further background, copending and commonly assigned U.S. application Ser. No. 14/857,873, filed Sep. 18, 2015 and incorporated herein by reference, describes a data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM), in which sampled groups of the memory cells are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
Another type of cell failure referred to as a “stuck bit” has been observed in modern 1T-1C ferroelectric memory cells. In the arrangement of cell 2jk described above relative to FIGS. 2a and 2b, these stuck bit failures are exhibited by cells that return a “1” data state regardless of their programmed state. Stated another way, a stuck cell is exhibited by an instance of cell 2jk programmed to a “0” data state (the “+1” polarization state of FIG. 1a), but that returns a “1” data state when read, as though it were programmed to the “−1” polarization state. It is believed that an instance of cell 2jk that is “stuck” in this manner has a defect in its capacitor 6 causing it to leak charge from the pulse applied to its plate line PL through pass transistor 4, increasing the signal at its bit line BLk and appearing as a “1” data state. These stuck bits cannot be programmed to a “0” data state that is sufficiently strong to return the “0” data state when read, for reasonable levels of reference voltage VREF. This failure mechanism of the stuck, or leaky, bit has been observed to develop over the operating life of the FRAM, for example as may be accelerated by a high temperature bake as commonly used to evaluate the reliability of a population of FRAM devices.
As known in the art, the sensing of 2T-2C cells in normal operation is based on a differential signal at complementary bit lines that are coupled to the accessed FRAM cell. By way of further background, a time-zero measurement of the slope of a cumulative fail bit distribution of half-cells in the 2T-2C memory, versus the reference voltage VREF is known in the testing of 2T-2C FRAM cells is used as a measure of time-zero polarization.